1. Field
Example embodiments relate to a vertical-type semiconductor device, a method of manufacturing the vertical-type semiconductor device and a method of operating the vertical-type semiconductor device. More particularly, example embodiments relate to a semiconductor device having a vertical-type pillar transistor suitable for a cell array structure, a method of manufacturing the semiconductor device and a method of operating the semiconductor device.
2. Description of the Related Art
Generally, as semiconductor devices become highly integrated, dimensions of active regions are reduced, and channel lengths of MOS transistors formed in the active regions are reduced. As the channel length of the MOS transistor is reduced, electric fields or potentials in the channel regions are dramatically affected by a source or drain, and the short channel effects arise. When the short channel effects occur, a leakage current is increased, a threshold voltage is decreased and a current effected by a drain voltage is increased. Accordingly, it becomes difficult to control the MOS transistor by a gate.
Thus, methods of scaling down devices formed on a substrate and improve characteristics of the device has been researched. For example, a vertical-type pillar transistor including in a channel region formed in a vertical direction with respect to a substrate has been researched. That is, in the vertical-type pillar transistor, a semiconductor pattern having a pillar shape on the substrate is used as the channel region. Even though a horizontal area in the substrate is not widened, the height of the semiconductor pattern having a pillar shape may be controllable to be increased to provide a desired channel length.
Since the vertical-type pillar transistor is formed in the semiconductor pattern, not in the bulk substrate, characteristics of the semiconductor pattern may be very important for performances of the transistor. That is, when the semiconductor pattern has any crystal defect, leakage current properties and threshold voltages in the vertical-type pillar transistor formed in each of the semiconductor patterns may not be uniform. However, because it is considerably more difficult than the bulk substrate to form the semiconductor pattern without any crystal defect, it may be not easy to ensure electrical properties of the vertical-type pillar transistors.
Additionally, processes of forming a gate and a source/drain in the pillar-shaped semiconductor pattern are considerably more complicated than those in the substrate. Further, when the vertical-type pillar transistors are formed to have an array structure, more complicated processes need to be additionally performed, such that the incidence of process failures increases. Accordingly, it may be difficult to manufacture a memory device of an array structure including the vertical-type pillar transistors.
Further, in order to manufacture a highly-integrated semiconductor memory device including the vertical-type pillar transistor, a method of reducing dimension of the substrate for each unit cell and providing a sufficient process margin is required.